A prior art CMOS buffer circuit is illustrated in FIG. 1 with a TTL input node V.sub.IN receiving input data signals of TTL high and low potential levels and at least one CMOS output node V.sub.OUT delivering output data signals at CMOS high and low potential levels. The CMOS buffer circuit incorporates multiple invertor stages coupled between the high potential rail V.sub.CC and the low potential rail GND. Each stage includes a pullup transistor element coupled to the high potential rail V.sub.CC, and a pulldown transistor element coupled to the low potential rail GND, an input node, and an output node.
For example, the first stage is composed of pullup transistor element P1 and pulldown transistor element N1 providing a data input stage. The fourth stage is composed of pullup transistor element P4 and pulldown transistor element N4 and provides a data output stage. In this example each of the pullup transistor elements P1, P2, P3 and P4 is a PMOS transistor element, while each of the pulldown transistor elements N1, N2, N3 and N4 is an NMOS transistor element.
The CMOS rail voltages are typically GND 0v and V.sub.CC 5v. The TTL high and low potential levels of input data signals applied at the TTL input node V.sub.IN however may only be in the range of for example 0v and 3v. In the worst case, the TTL data input signal swing may be even less. The initial stages of the buffer circuit must therefore change or translate the TTL input signal voltage swing to the full CMOS rail-to-rail signal voltage swing.
A problem encountered in the TTL to CMOS translation is that the non-rail TTL high potential level applied at the TTL input node V.sub.IN is typically insufficient to turn off the PMOS pullup transistor element Pl. The PMOS transistor element begins conducting with a threshold voltage across the source to gate junction greater than for example 1v. With a V.sub.CC rail of 5v and a TTL high potential level in the range of 2 to 3 volts applied at the TTL input node, PMOS pullup transistor element Pl remains conducting. This unwanted power supply current during the static high TTL data signal potential level at the input is referred to as the leakage current, quiescent current, static high current, or simply static current I.sub.CCt.
In order to avoid the static high current, one prior art solution is to introduce one or more voltage drop threshold components in series with the PMOS pullup transistor element between the pullup transistor element and the high potential rail. For example, a stack of three diodes might be coupled between transistor element Pl and V.sub.CC. With PN junction diodes the rail potential at the source of PMOS transistor element Pl is therefore reduced from 5v to approximately 3v. With a TTL high potential level applied at the TTL input node, the source to gate voltage threshold across transistor element Pl is reduced to substantially zero along with the static high current I.sub.CCt.
With a TTL low potential level applied at the TTL input node however, pullup transistor element Pl can no longer pullup the output node of the first stage to the high potential rail. Voltage drop threshold components must therefore be coupled in series with the pullup transistor element P2 of the second stage in order to avoid static current through the second stage. For example a stack of two diodes might be coupled in series between PMOS pullup transistor element P2 and the high potential rail V.sub.CC. A further voltage drop threshold component may be necessary in the third stage for example a single diode coupled between PMOS pullup transistor element P3 and the V.sub.CC rail.
Successive stages thus boost the data signal high potential level from the TTL high voltage level to the full CMOS high potential rail voltage of, for example 5v. Level translation is achieved while eliminating static current I.sub.CCt at each stage. However, the successive threshold components increase propagation delay of data signals through the buffer circuit.
In order to maintain switching speed and limit propagation delay during AC performance, a specified level of static high current I.sub.CCt is normally tolerated in DC performance. This is accomplished without using threshold components. Instead, the size of the PMOS pullup transistor elements in initial stages is substantially reduced in order to reduce in turn the I.sub.CCt. In pure CMOS circuits the PMOS pullup transistor element is normally substantially larger than the corresponding NMOS pulldown transistor element because of the greater conductivity of NMOS transistor elements. In contrast, at the first stage or data input stage of the buffer circuit of FIG. 1, pullup transistor element Pl is for example a 25u channel width PMOS transistor element while the pulldown transistor element N1 is a 100u channel width NMOS transistor element. At stage 2 transistor elements P2 and N2 are PMOS and NMOS transistor elements with equal 125u channel widths. By the third stage the respective sizes of the pullup and pulldown transistor elements return to a more standard ratio with a 500u channel width PMOS transistor element P3 and a 250u channel width NMOS transistor element N3. The output node from the third stage P3, N3 drives the final large pullup and pulldown transistor elements of the data output stage, a 1600u channel width PMOS transistor element P4 and a 1000u channel width NMOS transistor element N4. By the output of the third stage however the TTL high and low potential level signals have been translated to the full CMOS high and low potential levels, 0v and 5v, the voltages of the high and low potential rails. This is accomplished while maintaining AC performance signal propagation speed but with a static current I.sub.CCt specification of 1.5mA. The problem of simultaneously reducing or eliminating I.sub.CCt while maintaining switching speed has yet to be solved in the prior art.